1. Field of the Invention
The present invention relates to a read-only memory (ROM) and a method for operational control of the ROM, and more specifically to a ROM having a built-in self-test (BIST) circuit and a method for operational control of the ROM.
2. Description of the Prior Art
In accordance with the rapid development of electronic technologies, many complicated circuits, such as read-only memory (ROM), can be integrated into an integrated circuit (IC) to save space in an electronic apparatus having complicated design. The importance of testing in the manufacture of semiconductor IC chips has escalated because of ever increasing circuit speed and density. Built-in self-test (BIST) is one of the methods known to those of ordinary skill in the art for testing memory arrays on an IC for manufacturing defects.
Please refer to FIG. 1, which is a block diagram of a read-only memory (ROM) 10 with a BIST circuit 11 according to the prior art. The ROM 10 has a BIST circuit 11 and a ROM array 12. The ROM array 12 has a plurality of memory cells. Each of the memory cells of the ROM array 12 is used to store 1-bit binary data, i.e. “0” or “1”. The BIST circuit 11 is used to verify the data read from the ROM array 12. The BIST circuit 11 has a BIST controller 14, a compressor 16, and a verification circuit 18. The BIST controller 14 controls the operations of the ROM array 12, the compressor 16, and the verification circuit 18. When the BIST circuit 11 verifies the data Ds read from the ROM array 12, the BIST controller 14 commands the ROM array 12 to output data Ds to the compressor 16. Then, the compressor 16 compresses the output data Ds into compressed data Dc and transmits the compressed data Dc to the verification circuit 18. The verification circuit 18 is a specific circuit that is uniquely designed for the data stored in the ROM array 12. The verification circuit 18 is capable of verifying the data Ds read from the ROM array 12 by checking the compressed data Dc.
However, it is disadvantageous for the manufacturer to modify the data stored in the ROM array 12 because the verification circuit 18 must be re-designed if the data of the ROM array 12 is changed. Please refer to FIG. 2, which is a diagram showing a plurality of photo masks 21-27 for manufacturing the ROM 10 on a wafer 20. The wafer 20 is a silicon substrate, and the ROM 10 is one of the dies formed on the wafer 20. The photo masks 21-27 are used to process semiconductor procedures, such as exposure and etching, to from the circuit of the ROM 10 on the wafer 20. The layouts of the photo masks 21-27 establish the structure of the ROM 10. However, once the data of the ROM 10 is determined, making changes to the data is a difficult, time consuming, and an expensive undertaking. If the original data is faulty or needs to be updated, manufacturing an entirely new ROM is necessary. Hence, all of the photo masks 21-27 may need to be replaced.